The present invention relates to demodulator circuits for demodulating frequency modulated (FM) signals.
Referring to FIG. 1 of the accompanying drawings, a frequency modulated radio frequency (RF) signal is conventionally received by a receiver 1 from an antenna 2, and processed by the receiver 1 to produce an FM signal at a intermediate frequency which is lower than the RF carrier frequency. The IF modulated signal is then filtered by an IF band pass filter 4 and amplitude limited to a constant amplitude by a hard limiter 5. The constant amplitude signal is then fed to a detector 6 for demodulation by multiplying the signal by its time derivative. This operation makes the product amplitude proportional to both the signal""s amplitude and angular frequency (intermediate frequency IF plus FM frequency deviation). Since the FM IF signal has a constant amplitude, due to the hard limiter 5, the product signal has an amplitude proportional to the frequency deviation and the modulation signal can easily be recovered after a low-pass filter removes the signal components at multiples of the IF frequency.
Integration of FM detectors into semiconductor devices requires the use of accurate delay elements or filters with well controlled phase characteristics to generate the time-derivative approximation or else excessive DC offsets will occur.
Coincidence detectors in use today typically employ passive resonator components and a high-pass filter to provide the 90 degrees phase shift. The resonator circuit is often trimmed during production to provide low DC off-set.
Another detector variant in use when the FM-signal frequency (i.e. the IF signal) is high compared to the base-band signal is a digital detector based on a digital delay line (one or more latches) as differentiator. This delay line may be clocked by an accurate clock and hence result in a detector with an inherently low DC offset.
Another approach is to convert the analogue signal to a digital signal (A/D) and perform the FM detection in a digital signal processor DSP or other digital circuit.
In order to support on-chip intermediate frequency (IF) filters, it is convenient to use a low IF compared to the symbol rate (e.g. 3 MHz IF and 1 Msym/s symbol rate). This makes the use of a digital delay line impractical.
The most practical FM detector, when the IF frequency is just a few times the symbol rate, is a coincidence, or quadrature, detector, as illustrated in FIG 2. This detector requires three building blocks in addition to a post-detector low-pass filter (PDF); a multiplier 8, a delay element 9, and a 90xc2x0 (xcfx80/2) phase shifter 10.
The delay element 9 delays the incoming signal by a predetermined time, the phase shifter 10 produces a 9020  phase shift in this delayed signal, and then the delayed and shifted signal is multiplied with the input signal by the multiplier 8. The multiplier 8 can be provided by an exclusive-OR gate, or by a NAND gate. This may mean that the incoming signals to the multiplier will need to be conditioned.
The 90xc2x0 (xcfx80/2) coincidence-detector phase shifter 10 is typically implemented as a high-pass filter operating well below its corner frequency, hence providing near, but not quite, 90xc2x0 phase shift but also severely attenuating the signal amplitude. In addition, the phase shift is not accurate and some returning of the delay element is needed to compensate for the finite phase error.
According to one aspect of the present invention, there is provided a frequency modulated signal demodulator circuit including a phase shift element and a time delay element which operate on an input signal, wherein both the phase shift element and the time delay element are provided by a gyrator component.
According to a second aspect of the present invention, there is provided a demodulator circuit for demodulating a frequency modulated signal, the circuit comprising:
an input for receiving a frequency modulated input signal;
a gyrator which is connected to receive the modulated input signal and is operable to produce a gyrator output signal which is delayed and phase-shifted with respect to the input signal; and
a multiplier which is connected to receive the input signal and gyrator output signal and is operable to produce an output signal equivalent to the product of those received signals.